1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and, more particularly to a semiconductor integrated circuit having electrode pads which are arranged in an array-like form on its surface. And another invention relates to a printed circuit board having the semiconductor integrated circuit mounted thereon, and an electronic apparatus including the printed circuit board.
2. Description of the Related Art
In a semiconductor integrated circuit, a printed circuit board is loaded with a semiconductor chip such as an LSI (Large Scale Integrated Circuit), the semiconductor chip and the printed circuit board are packed in the form of a semiconductor package. Power supply electrode pads and ground electrode pads are provided on the bottom surface of the semiconductor package. The power supply electrode pads provide power supply potential supplied to the semiconductor chip, and ground electrode pads connect the semiconductor chip to the ground potential (ground) on the external circuit side.
In recent years, the circuit scale of semiconductor integrated circuits is enlarging. Along with the enlargement of the circuit scale of the semiconductor integrated circuits, the number of pins necessary for the connection between a semiconductor integrated circuit and an external circuit is increasing. For this reason, there have been developed the semiconductor integrated circuits each having a bottom surface on which a plurality of electrode pads are arranged in an array-like form. The electrode pads are power supply electrode pads connected to a power supply, ground electrode pads connected to the ground and signal electrode pads through which signals are inputted/outputted.
Heretofore, an arrangement of the power supply electrode pads and the ground electrode pads in the semiconductor integrated circuit has been determined by taking into consideration easiness of the circuit design of the semiconductor integrated circuit, an allowable current value of an output buffer for an output signal, and the like. The relative positional relationship between the power supply electrode pads and the ground electrode pads has not particularly been taken into account.
On the other hand, there is known the technique in which a decoupling capacitor is provided on a printed circuit board. It is provided in order to reduce the current noise which is propagated through power supply wiring or ground wiring to be inputted to a semiconductor chip and the radiation noise of the electromagnetic waves which are radiated along with the operation of a semiconductor integrated circuit. In the technique, it is important the position of the decoupling capacitor on the printed circuit board in the reduction of the noise. It seems to be good to be arranged near the place where more noise is occurred.
However, in the above-mentioned electrode pads, the position of the decoupling capacitor becomes far from the power supply electrode pads and the ground electrode pads of the semiconductor integrated circuit, or interferes with other wiring patterns depending on the wiring pattern of the printed circuit board. The position of the power supply electrode pads and the ground electrode pads related to the portion of the decoupling capacitor are determined only on the basis of the convenience of the semiconductor integrated circuit. As a result, there is encountered a problem in that the geometrical arrangement of individual power supply electrode pads and the ground electrode pads can not be made to accommodate a connection to the decoupling capacitor. Thus, the semiconductor integrated circuits in which the higher speed of the operating frequency is remarkably progressing, such as CPUs (Central Processing Units) and microprocessors, have a problem in that there is increased radiation noise due to the electromagnetic waves radiated from a printed circuit board and an electronic apparatus loaded with the printed circuit board. As a result, it becomes impossible to meet the standards for the unnecessary radiation noise which are regulated in various countries.
In order to solve the above-mentioned problem, there is disclosed the technique about a semiconductor integrated circuit in a published application (JP 2000-307005 A). In the semiconductor integrated circuit, a plurality of ground electrode pads and a plurality of power supply electrode in the semiconductor package are concentratedly arranged at the central portion of the bottom surface of the semiconductor package so as to be opposed to each other, and these electrode pads are connected to a decoupling capacitor through through-opening portions. According to this structure, it is possible to reduce the radiation noise of the electromagnetic waves radiated from the semiconductor integrated circuit.
In addition, in another published application (JP 2001-44591 A, JP 2001-284483 A), there is disclosed the technique in which a decoupling capacitor is provided within a printed circuit board inside a semiconductor package. Power supply vias and ground vias are arranged in lattice so as to be adjacent to each other and the decoupling capacitor is connected to power supply terminals of a semiconductor chip through the power supply vias and the decoupling capacitor is connected to ground terminals through the ground vias. Thus, the magnetic field generated by the current flow through the power supply vias and the magnetic field generated by the current flow through the ground vias cancel each other to reduce the inductance between the semiconductor chip and the decoupling capacitor, so that the decoupling capacitor effectively absorb the noise.
However, the above-mentioned prior arts have a following problem. In the technique disclosed in JP 2000-307005 A, the decoupling capacitor is directly formed on the rear surface of the printed circuit board having the semiconductor chip mounted on its surface. Accordingly, the decoupling capacitor is affected by parasitic capacitance with mounting on the printed circuit board, and it will be decrease the function of the decoupling capacitor. In addition, in the techniques disclosed in JP 2001-44591 A and JP 2001-284483 A, the decoupling capacitor is self-contained in the printed circuit board within the semiconductor package. For this reason, in those conventional techniques, there is encountered a problem in that after completion of the packaging of the semiconductor package, it is impossible to change the characteristics of the decoupling capacitor. Consequently, these semiconductor integrated circuits are limited in application of use thereof and hence are poor in wide application.